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PIC16LF1713 bảng dữ liệu(PDF) 76 Page - Microchip Technology |
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PIC16LF1713 bảng dữ liệu(HTML) 76 Page - Microchip Technology |
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76 / 483 page  PIC16(L)F1717/8/9 DS40001740B-page 76 2014-2015 Microchip Technology Inc. 6.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. IRCF<3:0> bits of the OSCCON register are modified. 2. If the new clock is shut down, a clock start-up delay is started. 3. Clock switch circuitry waits for a falling edge of the current clock. 4. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. The new clock is now active. 6. The OSCSTAT register is updated as required. 7. Clock switch is complete. See Figure 6-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 6-1. Start-up delay specifications are located in the oscillator tables of Section 34.0 “Electrical Specifications” . |
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