THS12082CDAR datasheet(13/44 Pages) TI2

13 / 44 page

THS12082

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS271B – MAY 2000 – REVISED DECEMBER 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

reading data from the FIFO

The THS12082 informs the connected processor via the digital output DATA_AV (data available) that a block

of conversion values is ready to be read. The block size to be read is always equal to the setting of the trigger

level. The selectable trigger levels depend on the number of selected analog input channels. For example, when

choosing one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate

the principle of reading the data.

In Figure 5, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means

that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 5. Trigger Level 1 Selected

In Figure 6, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means

that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 6. Trigger Level 4 Selected

In Figure 7, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means

that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 7. Trigger Level 8 Selected

In Figure 8, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means

that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 8. Trigger Level 14 Selected

READ is always the logical combination of CS0, CS1 and RD.

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