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74VHC27 bảng dữ liệu(PDF) 1 Page - STMicroelectronics |
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74VHC27 bảng dữ liệu(HTML) 1 Page - STMicroelectronics |
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1 / 7 page ![]() 74VHC27 TRIPLE 3-INPUT NOR GATE PRELIMINARY DATA June 1999 PIN CONNECTION AND IEC LOGIC SYMBOLS s HIGH SPEED: tPD = 4.1 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =2 µA (MAX.) at TA =25 oC s HIGH NOISE IMMUNITY: VNIH =VNIL =28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 27 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74VHC27 is an advanced high-speed CMOS TRIPLE 3-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provides high noise immunity and stable output. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ORDER CODES : 74VHC27M 74VHC27T M (Micro Package) T (TSSOP Package) ® 1/7 |
Số phần tương tự - 74VHC27 |
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Mô tả tương tự - 74VHC27 |
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