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STM32H523CCK7 bảng dữ liệu(PDF) 38 Page - STMicroelectronics

tên linh kiện STM32H523CCK7
Giải thích chi tiết về linh kiện  Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS
PDF  228 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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STM32H523CCK7 bảng dữ liệu(HTML) 38 Page - STMicroelectronics

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Functional overview
STM32H523xx
38/228
DS14540 Rev 1
3.21
Delay block (DLYB)
The delay block (DLYB) is used to generate an output clock dephased from the input clock.
The phase of the output clock must be programmed by the user application. The output
clock is then used to clock the data received by another peripheral such as an SDMMC or
Octo-SPI interface. The delay is voltage and temperature dependent, that may require the
application to re-configure and recenter the output clock phase with the received data.
The delay block main features are:
•
Input clock frequency ranging from 25 to 250 MHz
•
Up to 12 oversampling phases
3.22
Analog-to-digital converter (ADC1 and ADC2)
The devices embed two successive approximation analog-to-digital converters.
Table 5. ADC features
Mode/feature
ADC1
ADC2
Resolution
12 bit
Maximum sampling speed
up to 5 Msps (12-bit resolution)
Dual mode operation
X
Hardware offset calibration
X
Hardware linearity calibration
-
Single-end input
X
Differential input
X
Injected channel conversion
X
Oversampling
Up to x256
Data register
16 bits
Data register FIFO depth
3 stages
DMA support
X
Parallel data output to ADF
-
Offset compensation
X
Gain compensation
-
Number of analog watchdogs
3
Option register
X



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