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STM32H523CCI7 bảng dữ liệu(PDF) 49 Page - STMicroelectronics

tên linh kiện STM32H523CCI7
Giải thích chi tiết về linh kiện  Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS Arm Cortex -M33 32-bit MCUTrustZone FPU, 375 DMIPS
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32H523CCI7 bảng dữ liệu(HTML) 49 Page - STMicroelectronics

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DS14540 Rev 1
49/228
STM32H523xx
Functional overview
57
3.34
Improved inter-integrated circuit (I3C)
The I3C interface handles communication between the MCU and others, like sensors and
host processor(s), all connected on an I3C bus.
The peripheral implements the required features of the MIPI I3C specification v1.1. It can
control I3C bus-specific sequencing, protocol, arbitration and timing, and can act as
controller (formerly known as master) or as target (formerly known as slave). When acting
as controller the peripheral improves the features of the I2C interface, preserving some
backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C
fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that the latter does not
perform clock stretching.
The I3C peripheral can be used with DMA to off-load the CPU.
Table 8. I3C peripheral controller/target features versus MIPI v1.1
Feature
MIPI
v1.1
When
controller
When
target
Comments
I3C SDR message
X
X
X
-
Legacy I2C message (Fm/Fm+)
X
X
-
Mandatory when controller, and the I3C bus is
mixed with (external) legacy I2C target(s).
Optional in MIPI v1.1 when target.
HDR DDR message
X
-
-
Optional in MIPI v1.1
HDR-TSL/TSP, HDR-BT
X
-
-
Dynamic address assignment
X
X
X
-
Static address
X
X
-
No (intended) support of I3C peripheral as a
target on an I2C bus.
Grouped addressing
X
X
-
Optional in MIPI v1.1
CCCs
X
X
X
Mandatory and some optional CCCs supported.
Error detection and recovery
X
X
X
-
In-band interrupt (with MDB)
X
X
X
-
Secondary controller
X
X
X
-
Hot-join mechanism
X
X
X
-
Target reset
X
X
X
-
Synchronous timing control
X
X
-
Optional in MIPI v1.1
Asynchronous timing control 0
X
X
-
Asynchronous timing control 1, 2, 3
X
-
-
Device to device tunneling
X
X
-
Multi-lane data transfer
X
X
-
Monitoring device early termination
X
-
-



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