A

2

B

3

C

7

D

6

Y

5

OE

1

SN74LVC1G99

SCES609G – SEPTEMBER 2004 – REVISED NOVEMBER 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Function Table

INPUTS

OUTPUT

OE

D

C

B

A

Y

L

L

L

L

L

L

L

L

L

L

H

H

L

L

L

H

L

L

L

L

L

H

H

H

L

L

H

L

L

L

L

L

H

L

H

L

L

L

H

H

L

H

L

L

H

H

H

H

L

H

L

L

L

H

L

H

L

L

H

L

L

H

L

H

L

H

L

H

L

H

H

L

L

H

H

L

L

H

L

H

H

L

H

H

L

H

H

H

L

L

L

H

H

H

H

L

H

H or L

H or L

H or L

H or L

Z

Logic Diagram (Positive Logic)

2

Submit Documentation Feedback

Copyright © 2004–2013, Texas Instruments Incorporated

Product Folder Links: SN74LVC1G99