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DLG4137 bảng dữ liệu(PDF) 3 Page - OSRAM GmbH

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DLG4137 bảng dữ liệu(HTML) 3 Page - OSRAM GmbH

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 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
Appnote 28
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
3
May 31, 2000-13
If small wire cables are used, good engineering practice is to
calculate the wire resistance of the ground and the +5 volt
wires. More than 0.2 volt drop (at 100 ma per digit) should be
avoided, since this loss is in addition to any inaccuracies or load
regulation of the power supply.
The 5 volt power supply for the DLO4135/DLG4137 should be
the same one supplying the VCC to all logic devices. If a separate
power supply must be used, then local buffers should be used
on all the inputs. These buffers should be powered from the dis-
play power supply. This precaution is to avoid line transients or
any logic signals to be higher than VCC during power up.
Figure 5. Block diagram of the Intel 8031 controller
Interfacing
For an eight digit display using the DLO4135/DLG4137, inter-
facing to a single chip microprocessor such as the 8748, is easy
and straight forward. One approach may be to dedicate one
port for the seven data signals and another 8-bit port for the
write signals. The schematic is shown in Figure 6.
I/O or Memory Mapped System
For a memory mapped system using a processor such as the
8080 or 8085, the interfacing is also straight-forward. Each dis-
play is treated as a memory location with its own address, like
another I/O or RAM location. See Figure 7.
Figure 6. DLO4135/DLG4137 with 8748
8
8
3
8
8
LATCH
BUFFER
EPROM
27xx
DECODER
D Ø
D 7
P3.0
P3.1
P3.2
P3.6
PØ
ALE
8031
A0-A7
OE
PSEN
x
x
x
x
x
8748
6 5 4 3 2 1 0
P2
P1
+
D0
D1
D2
D3
D4
D5
D6
7
6
5
4
3
2
1
0
DLO 4135
DLG 4137
Subroutine to Load an 8-digit Display using the DLO4135/
DLG4137
; DATA IN RAM 10H-17H
(MSD-LSD)
INIT
ORL
P1,#0FFH
; PORT 1 ALL HIGH (WRITE)
ORL
P2,#00H
; PORT 2 ALL LOW (DATA)
MOV
R1,#OFH
; RAM ADDRESS—1
MOV
R2,#0FEH
; WRITE PULSE
MOV
R3,#08H
; COUNTER
START:
INC
R1
; INCREMENT RAM POINTER
DATA:
MOV
A,@R1
; FETCH DATA FROM RAM
OUTL P2,A
; LOAD PORT 2
MOV
A,R2
; RECALL WRITE
RR
A
; SHIFT A TO NEXT WRITE
MOV
R2,A
; SAVE WRITE
WRITE: OUTL P1,A
; SEND WRITE PULSE
MOV
A,#OFFH
; WAIT
OUTL P1,A
; RESET WRITE PULSE
DJNZ
R3,START
; LOAD COMPLETE?
RET
; RETURN TO MAIN PROGRAM
Figure 7. Block diagram for 8-digit DLO4135/DLG4137
Routine for an 8-Digit Display using the DLO4135/DLG4137
and 8085 or 8080 Microprocessor
; DATA TO BE DISPLAYED IS IN
; A0 (LSD) THRU A7 (MSD)
;
; DISPLAY ADDRESS C00X
; LSD IS RIGHT MOST DIGIT
;
; DOES NOT SAVE REG A,B,H,L,D,E
;
DADD EQU
0A000H
; DATA ADDRESS LOCATION
DPAD
EQU
0C000H
; DISPLAY ADDRESS
LOCATION
LEN
EQU
08H
; DISPLAY LENGTH
;
ORG
100H
;
DISP:
LXI
H,DADD
; LOAD DATA ADDRESS
LXI
D,DPAD
; LOAD DISPLAY ADDRESS
MVI
B,LEN
; LOAD DISPLAY LENGTH
DISP1: MOV
A,M
; GET DATA
XCHG
; XCHG H/L & D/E
MOV
M,A
; LOAD DISPLAY FROM REG A
XCHG
; RESTORE H/L & D/E
INX
D
; INCREMENT DISPLAY ADDRESS
INX
H
; INCREMENT DATA ADDRESS
DCR
B
; DECREMENT LENGTH COUNTER
JNZ
DISP1
; END OF DISPLAY?
RET
; RETURN TO MAIN PROGRAM
8080
or
8085
System
Data
I/OW
Address
Eight DLX413X
A0
A1
A2



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