SN74ALVC08-Q1

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCES491C − SEPTEMBER 2003 − REVISED JANUARY 2008

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Qualified for Automotive Applications

D ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D Operates From 1.65 V to 3.6 V

D Max t

pd of 2.9 ns at 3.3 V

D ±24-mA Output Drive at 3.3 V

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

description/ordering information

The SN74ALVC08 quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation.

The device performs the Boolean function Y

+ A • Bor Y + A ) B in positive logic.

ORDERING INFORMATION†

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

40

°Cto85°C

SOIC − D

Tape and reel

SN74ALVC08IDRQ1

ALVC08I

−40

°C to 85°C

TSSOP − PW

Tape and reel

SN74ALVC08IPWRQ1

VA08I

† For the most current package and ordering information, see the Package Option Addendum at the end of

this document, or see the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

OUTPUT

Y

H

H

H

L

XL

X

L

L

logic diagram, each gate (positive logic)

A

B

Y

Copyright

© 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

VCC

4B

4A

4Y

3B

3A

3Y