MPC5554MZP112 datasheet(38/58 Pages) NXP

38 / 58 page

MPC5554 Microcontroller Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

3.13.7

eMIOS Timing

Figure 17. eMIOS Timing

3.13.8

DSPI Timing

Table 25. eMIOS Timing 1

1 eMIOS timing specified at: V

DDEH = 3.0–5.25 V and TA = TL to TH.

Spec

Characteristic

Symbol

Min.

Max.

Unit

eMIOS input pulse width

tMIPW

4—

tCYC

eMIOS output pulse width

tMOPW

1 2

2 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise

and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR).

—tCYC

Table 26. DSPI Timing1’ 2

Spec

Characteristic

Symbol

80 MHz

112 MHz

132 MHz

Unit

Min.

Max.

Min.

Max.

Min.

Max.

SCK cycle time3, 4

tSCK

24.4 ns

2.9 ms

17.5 ns

2.1 ms

15.2 ns

1.7 ms

—

PCS to SCK delay5

tCSC

—

After SCK delay6

tASC

—

SCK duty cycle

tSDC

(tSCK  2)

– 2 ns

(tSCK  2)

+ 2 ns

(tSCK  2)

– 2 ns

(tSCK  2)

+ 2 ns

(tSCK  2)

– 2 ns

(tSCK  2)

+ 2 ns

Slave access time

(SS active to SOUT driven)

—

Slave SOUT disable time

(SS inactive to SOUT Hi-Z, or invalid)

tDIS

—

7PCSx to PCSS time

tPCSC

4—

—

8PCSS to PCSx time

tPASC

5—

—

eMIOS

output

eMIOS input

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