SN74ACT16374Q-EP

16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP

WITH 3-STATE OUTPUTS

SCAS679B – MAY 2002 – REVISED JULY 2002

4

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 1)

TA = 25°C

MIN

MAX

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

0

65

0

65

MHz

t

Pulse duration

CLK low

7.5

7.5

ns

tw

Pulse duration

CLK high

4.5

4.5

ns

tsu

Setup time, data before CLK

↑

6.5

6.5

ns

th

Hold time, data after CLK

↑

1

1

ns

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

TA = 25°C

MIN

MAX

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

UNIT

fmax

65

65

MHz

tPLH

CLK

Q

5.1

8.8

10.9

5.1

13.2

ns

tPHL

CLK

Q

5.3

8.8

10.9

5.3

13.1

ns

tPZH

OE

Q

3.7

8.4

10.5

3.7

12.7

ns

tPZL

OE

Q

4.4

9.7

11.9

4.4

14.3

ns

tPHZ

OE

Q

5.4

7.9

9.8

5.4

10.9

ns

tPLZ

OE

Q

4.9

7.2

9.1

4.9

10.2

ns

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER

TEST CONDITIONS

TYP

UNIT

C d

Power dissipation capacitance per flip flop

Outputs enabled

CL =50 pF

f=1MHz

52

pF

Cpd

Power dissipation capacitance per flip-flop

Outputs disabled

CL = 50 pF,

f = 1 MHz

38

pF