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SN54ABT8543 bảng dữ liệu(PDF) 2 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
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SN54ABT8543 bảng dữ liệu(HTML) 2 Page - Texas Instruments

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SN54ABT8543, SN74ABT8543
SCAN TEST DEVICES WITH
OCTAL REGISTERED BUS TRANSCEIVERS
SCBS120E – AUGUST 1991 – REVISED JULY 1996
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
description (continued)
Data flow in each direction is controlled by latch-enable (LEAB and LEBA), chip-enable (CEAB and CEBA), and
output-enable (OEAB and OEBA) inputs. For A-to-B data flow, the device operates in the transparent mode
when LEAB and CEAB are both low. When either LEAB or CEAB is high, the A data is latched. The B outputs
are active when OEAB and CEAB are both low. When either OEAB or CEAB is high, the B outputs are in the
high-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses LEBA, CEBA, and OEBA.
In the test mode, the normal operation of the SCOPE
™ registered bus transceiver is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8543 is characterized for operation over the full military temperature range of –55
°C to 125°C.
The SN74ABT8543 is characterized for operation from –40
°C to 85°C.
FUNCTION TABLE†
(normal mode, each register)
INPUTS
OUTPUT
CEAB
OEAB
LEAB
A
B
L
L
L
L
L
L
LL
H
H
L
LH
X
B0‡
L
HX
X
Z
H
X
X
X
Z
† A-to-B data flow is shown. B-to-A data flow is similar but
uses CEBA, OEBA, and LEBA.
‡ Output level before the indicated steady-state input
conditions were established



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