PTH04040W

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SLTS238C – SEPTEMBER 2005 – REVISED JUNE 2010

ELECTRICAL CHARACTERISTICS

TA = 25°C, VI = 5 V, VO = 2.5 V, CI = 1000 µF, CO = 660 µF, and IO = IOmax (unless otherwise stated)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IO

Output current

60°C, 200 LFM airflow

0

60(1)

A

VI

Input voltage range

Over IO range

2.95(2)

5.5

V

VOtol

Set-point voltage tolerance

±2(3)

%VO

ΔRegtemp

Temperature variation

–40°C < TA < 85°C

±0.5

%VO

ΔRegline

Line regulation

Over VI range

±5

mV

ΔRegload

Load regulation

Over IO range

±5

mV

ΔRegtot

Total output variation

Includes set-point, line, load, –40°C

≤ TA ≤ 85°C

±3(3)

%VO

2.95

≤ VI ≤ 4.5 V

(3)

0.8

-

1.65

VO, ADJ

Output adjust range

V

4.5 < VI ≤ 5.5 V

(3)

0.8

-

2.5

RSET = 2.21 kΩ, VO = 2.5 V

93%

RSET = 5.49 kΩ, VO = 1.8 V

90%

VI = 5 V, IO = 45 A

RSET = 8.87 kΩ, VO = 1.5 V

88%

h

Efficiency

RSET = 17.4 kΩ, VO = 1.2 V

86%

RSET = 6.92 kΩ, VO = 1.65 V

92%

VI = 3.3 V, IO = 45 A

RSET = 8.87 kΩ, VO = 1.5 V

91%

RSET = 36.5 kΩ, VO = 1 V

87%

VR

VO ripple (peak-to-peak)

20-MHz bandwidth

All voltages

15

mVPP

IOtrip

Overcurrent threshold

Reset, followed by auto-recovery

90

A

trr

Recovery time

100

µS

1 A/µs load step, 50 to 100%

Transient response

IOmax, CO=660µF

ΔVtr

VO over/undershoot

200

mV

Margin up down adjust

From a given set-point voltage

±5%

%

IILmargin

Margin input current

Pin to GND

–8(4)

µA

IILtrack

Track input current (pin 18)

Pin to GND

–0.11(5)

mA

dV/dt

Track slew rate capability

|VTRACK – VO | ≤ 50 mV and V(TRACK) < VO(nom)

1

V/ms

On-threshold

2.6(6)

UVLO

Undervoltage lockout

Pin 8 open

V

Hysterisis

0.6(6)

Input high voltage (VIH), Referenced to GND

2.5

Open(7)

V

Inhibit control (pin 7)

Input low voltage (VIL), Referenced to GND

–0.2

0.5

Input low current (IIL), Pin to GND

0.5

mA

IIinh

Input standby current

Inhibit (pin 7) to GND

60

mA

f s

Switching frequency

Over VI and IO ranges

675

825

975

kHz

(1)

See SOA curves or consult factory for appropriate derating.

(2)

The nominal input voltage must be at least 2 × VO. Output voltage regulation is specified with an input voltage within ±10% from nominal

3.3 V or 5 V. For example, for VI = 5 V and VO = 2.5 V, the input can vary between 4.5 V and 5.5 V.

(3)

The set-point voltage tolerance is affected by the tolerance of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1%

with 100 ppm/°C or better temperature stability.

(4)

A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.

(5)

This control pin has an internal pull-up to VI. If it is left open-circuit the module operates when input power is applied. A small,

low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. See the Auto-Track

Application Information section for further guidance.

(6)

These are the default voltages. They may be adjusted using the UVLO Prog control input. See the UVLO Application Information section

for further guidance.

(7)

This control pin has an internal pull-up to VI. If it is left open-circuit the module operates when input power is applied. A small,

low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an external

pull-up on this pin. See the Inhibit Application Information section for further guidance.

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