PCM3060PW datasheet(20/48 Pages) TI2

20 / 48 page

www.ti.com

DOUT

0.5 V

DIN

1.4 V

BCK1/2

(Output)

SCKI1/2

(Input)

LRCK1/2

(Output)

(BCY)

(DIH)

(BCH)

(BCL)

(LRD)

(DIS)

(DOD)

(BCD)

T0248-01

Audio Interface Format

PCM3060

SLAS533B – MARCH 2007 – REVISED MARCH 2008

SYMBOL

PARAMETERS

MIN

TYP

MAX

UNIT

t(BCY)

BCK1/2 cycle time

1/64 fS

tw(BCH)

BCK1/2 high time

0.4 t(BCY)

0.5 t(BCY)

0.6 t(BCY)

tw(BCL)

BCK1/2 low time

0.4 t(BCY)

0.5 t(BCY)

0.6 t(BCY)

t(LRD)

LRCK1/2 delay time from BCK1/2 falling edge

t(DIS)

DIN setup time to BCK1/2 rising edge

t(DIH)

DIN hold time to BCK1/2 rising edge

t(DOD)

DOUT delay time from BCK1/2 falling edge

t(BCD)

BCK1/2 delay time from SCKI1/2 rising edge(1)

NOTE: Load capacitance of output is 20 pF.

(1)

This specification applies for SCKI1/2 when the frequency is less than 25 MHz.

Figure 25. Audio Data Interface Timing (Master Mode: BCK1/2 and LRCK1/2 work as Outputs)

The PCM3060 supports the following four interface formats in both slave and master modes, and they are

selectable independently for the ADC and DAC using serial mode control.

24-bit I2S format

24-bit left-justified format

24-bit right-justified format

16-bit right-justified format

All formats are provided in MSB-first, 2s complement data format.

Submit Documentation Feedback

Product Folder Link(s): PCM3060

PCM3060PW bảng dữ liệu(PDF) 20 Page - Texas Instruments

PCM3060PW bảng dữ liệu(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

bảng dữ liệu tải về

Link URL