PCM1850

PCM1851

SLES108 − MARCH 2004

www.ti.com

12

−100 −90 −80 −70 −60 −50 −40 −30 −20 −10

0

Signal Level – dB

TOTAL HARMONIC DISTORTION + NOISE

vs

SIGNAL LEVEL

100

1

0.1

0.01

0.001

10

Figure 17

SUPPLY CURRENT

PGA GAIN LINEARITY

Figure 18

0

5

10

15

20

25

30

16

36

56

76

96

SUPPLY CURRENT

vs

fSAMPLE CONDITION

ICC

fSAMPLE Condition – kHz

IDD

Figure 19

Gain Setting – dB

−11

−9

−7

−5

−3

−1

1

3

5

7

9

11

−11 −9 −7 −5 −3 −11

3

5

7

9

11

OVERALL GAIN

vs

GAIN SETTING

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted