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PCM1796DB.B bảng dữ liệu(PDF) 40 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER
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PCM1796DB.B bảng dữ liệu(HTML) 40 Page - Texas Instruments

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PCM1796
SLES100A − DECEMBER 2003 − REVISED NOVEMBER 2006
www.ti.com
40
FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL FILTER MODE
The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20. B4).
The external digital filter mode allows access to the majority of the PCM1796 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
–
–
–
–
–
–
–
–
Register 17
R/W
0
0
1
0
0
0
1
–
–
–
–
–
–
–
–
Register 18
R/W
0
0
1
0
0
1
0
–
FMT2
FMT1
FMT0
–
–
–
–
Register 19
R/W
0
0
1
0
0
1
1
REV
–
–
OPE
–
DFMS
–
INZD
Register 20
R/W
0
0
1
0
1
0
0
–
SRST
0
1
MONO
CHSL
OS1
OS0
Register 21
R/W
0
0
1
0
1
0
1
–
–
–
–
–
–
–
PCMZ
Register 22
R
0
0
1
0
1
1
0
–
–
–
–
–
–
ZFGR
ZFGL
NOTE: –: Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
Audio Data Format Select
000
16-bit right-justified format (default)
001
20-bit right-justified format
010
24-bit right-justified format
Other
N/A
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
Operation Speed Select
00
8 times WDCK (default)
01
4 times WDCK
10
16 times WDCK
11
Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and
the delta-sigma modulator. For example, if the external digital filter is 8
× oversampling, and the user selects
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8
×, resulting in an effective oversampling rate of 64×.
The 16
× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected
is 16
× WDCK, the system clock frequency must be over 256 fS.



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