PCM1737ESLASH2K.B datasheet(22/32 Pages) TI2

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PCM1737

FIGURE 11. Output Filter Frequency Response.

ANALOG OUTPUTS

The PCM1737 includes two independent output channels:

VOUTL and VOUTR. These are unbalanced outputs, each

capable of driving 3.1Vp-p typical into a 5k

Ω AC-coupled

load (VCC = +5V). The internal output amplifiers for VOUTL

and VOUTR are DC biased to a DC common-mode (or

bipolar zero) voltage, equal to VCC/2.

The output amplifiers include an RC continuous-time filter,

which helps to reduce the out-of-band noise energy present

at the DAC outputs due to the noise shaping characteristics

of the PCM1737’s delta-sigma D/A converters. The fre-

quency response of this filter is shown in Figure 11. By

itself, this filter is not enough to attenuate the out-of-band

noise to an acceptable level for most applications. An

external low-pass filter is required to provide sufficient out-

of-band noise rejection. Further discussion of DAC post-

filter circuits is provided in the Applications Information

section of this data sheet.

VCOML AND VCOMR OUTPUTS

Two unbuffered common-mode voltage output pins, VCOML

(pin 17) and VCOMR (pin 12), are brought out for decoupling

purposes. These pins are nominally biased to a DC voltage

level equal to VCC/2. These pins may be used to bias external

circuits, a voltage follower is required for buffering pur-

poses. Figure 12 shows an example of using the VCOML and

VCOMR pins for external biasing applications.

ZERO FLAG AND INFINITE ZERO DETECT MUTE

FUNCTIONS

The PCM1737 includes circuitry for detecting an all ‘0’ data

condition for the data input pin, DATA. This includes two

independent functions: Zero Output Flags and Zero Detect

Mute. Although the flag and mute functions are independent

of one another, the zero detection mechanism is common to

both functions.

Zero Detect Condition

Zero Detection for each output channel is independent from

the other. If the data for a given channel remains at a ‘0’

level for 1024 sample periods (or LRCK clock periods), a

Zero Detect condition exists for that channel.

Zero Output Flags

Given that a Zero Detect condition exists for one or more

channels, the Zero flag pins for those channels will be set to

a logic ‘1’state. There are Zero Flag pins for each channel,

ZEROL (pin 23) and ZEROR (pin 24). These pins can be

used to operate external mute circuits, or used as status

indicators for a microcontroller, audio signal processor, or

other digitally-controlled functions.

Infinite Zero Detect Mute

Infinite Zero Detect Mute is an internal logic function. The

Zero Detect Mute can be enabled or disabled using the INZD

bit of Control Register 18. The reset default is Zero Detect

Mute disabled, INZD = 0. Given that a Zero Detect Condi-

tion exists for one or more channels, the zero mute circuitry

will immediately force the corresponding DAC output(s) to

the bipolar zero level, or VCC/2.

100

10k

ANALOG FILTER RESPONSE

100k

10M

–10

–20

–30

–40

–50

–60

Frequency (Hz)

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