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LAN9252T/ML bảng dữ liệu(PDF) 49 Page - Microchip Technology

tên linh kiện LAN9252T/ML
Giải thích chi tiết về linh kiện  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252T/ML bảng dữ liệu(HTML) 49 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 49
LAN9252
4
RESERVED
RO
-
3:1
RESERVED
RO
-
0
Device Ready (READY)
When set, this bit indicates that the device is ready to be accessed. Upon
power-up, RST# reset, return from power savings states, EtherCAT chip level
or module level reset, or digital reset, the host processor may interrogate this
field as an indication that the device has stabilized and is fully active.
This rising edge of this bit will assert the Device Ready (READY) bit in
INT_STS and can cause an interrupt if enabled.
Note:
With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
Note:
This bit is identical to bit 27 of the Hardware Configuration Register
(HW_CFG).
RO
0b
Bits
Description
Type
Default



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