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LAN9252/ML bảng dữ liệu(PDF) 118 Page - Microchip Technology

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Giải thích chi tiết về linh kiện  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
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LAN9252
DS00001909A-page 118
 2015 Microchip Technology Inc.
10.2.6.5
Quad Address / Data Write
The SPI Quad Address / Data Write instruction inputs the instruction code one bit per clock and the address and data
bytes four bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 80 MHz. This
instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQADW instruction, E2h, is input into the
SIO[0] pin, followed by the two address bytes into the SIO[3:0] pins. The address bytes specify a BYTE address within
the device.
The data follows the address bytes. The data is input into the SIO[3:0] pins starting with the msn of the LSB. The remain-
ing nibbles are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are input. In
the event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is
not affected.
The SCS# input is brought inactive to conclude the cycle.
Figure 10-16 illustrates a typical single and multiple register dual address / data write.
FIGURE 10-16:
SPI QUAD ADDRESS / DATA WRITE
SPI Quad Address / Data Write Single Register
SCK (active high)
SIO0
0
11
X
Instruction
1
SIO1
SPI Quad Address / Data Write Multiple Registers
00
SCK (active low)
SCS#
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
X
1
7
1
8
1
9
2
0
1
7
1
8
1
9
2
0
SCK (active high)
SIO0 X
Instruction
SIO1
...
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
X
X
...
...
0
Data
D
5
D
4
D
1
Z
X
D
1
7
D
2
5
D
0
D
1
3
D
1
2
D
2
4
D
1
6
D
2
8
D
2
9
X
Data
D
6
D
2
D
1
4
D
1
8
D
2
6
D
3
0
D
7
D
3
D
1
5
D
1
9
D
2
7
D
3
1
Z
X
Z
X
Data
Data
D
9
D
8
D
2
1
D
2
0
D
1
0
D
2
2
D
1
1
D
2
3
SIO2
SIO3
...
...
...
...
Data 1...
Data m
Data m+1... Data n
D
5
D
4
D
1
D
0
D
1
3
D
1
2
D
1
7
D
2
5
D
2
4
D
1
6
D
2
8
D
2
9
Z
X
X
Data 1...
Data m
Data m+1... Data n
...
...
Data 1...
Data m
Data m+1... Data n
D
6
D
2
D
1
4
D
1
8
D
2
6
D
3
0
Z
X
...
...
Data 1...
Data m
Data m+1... Data n
D
7
D
3
D
1
5
D
1
9
D
2
7
D
3
1
Z
X
D
5
D
4
D
1
D
0
D
1
3
D
1
2
D
6
D
2
D
1
4
D
7
D
3
D
1
5
D
1
7
D
2
5
D
2
4
D
1
6
D
2
8
D
2
9
D
1
8
D
2
6
D
3
0
D
1
9
D
2
7
D
3
1
SIO2
SIO3
0
11
1
00
0
Address
d
e
c
A
1
3
Z
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Z
Z
Address
d
e
c
A
1
3
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Z
Z
Z
1
1



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