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LAN9252/ML bảng dữ liệu(PDF) 112 Page - Microchip Technology

tên linh kiện LAN9252/ML
Giải thích chi tiết về linh kiện  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
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LAN9252
DS00001909A-page 112
 2015 Microchip Technology Inc.
10.2.5.2
Quad I/O Read
The SPI Quad I/O Read instruction inputs the instruction code one bit per clock and the address and dummy bytes four
bits per clock and outputs the data four bits per clock. This instruction is supported in SPI bus protocol only with clock
frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQIOR instruction, EBh, is input into the
SIO[0] pin, followed by the two address bytes and 4 dummy bytes into the SIO[3:0] pins. The address bytes specify a
BYTE address within the device.
On the falling clock edge following the rising edge of the last dummy nibble, the SIO[3:0] pins are driven starting with
the msn of the LSB of the selected register. The remaining register nibbles are shifted out on subsequent falling clock
edges.
The SCS# input is brought inactive to conclude the cycle. The SIO[3:0] pins are three-stated at this time.
Figure 10-10 illustrates a typical single and multiple register quad I/O read.
FIGURE 10-10:
SPI QUAD I/O READ
SPI Quad I/O Read Single Register
SCK (active high)
SIO0
11
1
1
X
Instruction
1
SIO1
Data
SPI Quad I/O Read Multiple Registers
10
D
5
D
4
D
1
Z
X
SCK (active low)
SCS#
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
2
8
X
X
2
5
2
6
2
7
2
8
D
1
7
1
7
1
8
1
9
2
0
2
1
2
2
2
3
1
7
1
8
1
9
2
0
2
1
2
2
2
3
SCK (active high)
SIO0 X
Instruction
Address
SIO1
d
e
c
A
1
3
...
...
Z
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
X
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
1
7
1
8
1
9
2
0
2
1
2
2
2
3
...
...
...
...
x
x
x
x
x
x
x
x
Dummy
D
2
5
Data 1...
Data m
Data m+1... Data n
...
D
0
D
1
3
D
1
2
D
2
4
D
1
6
D
2
8
D
2
9
X
Data
D
5
D
4
D
1
D
0
D
1
3
D
1
2
D
1
7
D
2
5
D
2
4
D
1
6
D
2
8
D
2
9
Z
X
X
Data 1...
Data m
Data m+1... Data n
SIO2
Z
...
...
Data 1...
Data m
Data m+1... Data n
D
6
D
2
D
1
4
D
1
8
D
2
6
D
3
0
Z
X
SIO3
Z
...
...
Data 1...
Data m
Data m+1... Data n
D
7
D
3
D
1
5
D
1
9
D
2
7
D
3
1
Z
X
D
5
D
4
D
1
D
0
D
1
3
D
1
2
D
6
D
2
D
1
4
D
7
D
3
D
1
5
D
1
7
D
2
5
D
2
4
D
1
6
D
2
8
D
2
9
D
1
8
D
2
6
D
3
0
D
1
9
D
2
7
D
3
1
SIO2
D
6
D
2
D
1
4
D
1
8
D
2
6
D
3
0
SIO3
D
7
D
3
D
1
5
D
1
9
D
2
7
D
3
1
Z
X
Z
X
0
11
1
1
1
10
0
x
x
x
x
x
x
x
x
Dummy
x
x
x
x
x
x
x
x
Dummy
x
x
x
x
x
x
x
x
Dummy
Address
d
e
c
A
1
3
Z
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Z
Z
x
x
x
x
x
x
x
x
Dummy
x
x
x
x
x
x
x
x
Dummy
x
x
x
x
x
x
x
x
Dummy
x
x
x
x
x
x
x
x
Dummy
2
4
2
4
D
9
D
8
D
2
1
D
2
0
D
1
0
D
2
2
D
1
1
D
2
3



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