LAN9252SLASHML datasheet(269/329 Pages) MICROCHIP

tên linh kiện	LAN9252/ML

Giải thích chi tiết về linh kiện	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

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nhà sản xuất	MICROCHIP [Microchip Technology]

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 2015 Microchip Technology Inc.

DS00001909A-page 269

LAN9252

12.14.59.2 FMMUx Length Register

Note:

For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the

highest address.

12.14.59.3 FMMUx Logical Start Bit Register

12.14.59.4 FMMUx Logical Stop Bit Register

Offset:

FMMUx Base Address +4h-5h

Size:

16 bits

Bits

Description

ECAT

Type

PDI

Type

Default

15:0

Length

Offset from the first logical FMMU byte to the last FMMU Byte +

1 (e.g., if two bytes are used, then this parameter shall contain

2).

R/W

0000h

Offset:

FMMUx Base Address +6h

Size:

8 bits

Bits

Description

ECAT

Type

PDI

Type

Default

7:3

RESERVED

Write as 0.

00000b

2:0

Logical Start Bit

Logical starting bit that shall be mapped (bits are counted from

least significant bit (0) to most significant bit (7)).

R/W

000b

Offset:

FMMUx Base Address +7h

Size:

8 bits

Bits

Description

ECAT

Type

PDI

Type

Default

7:3

RESERVED

Write as 0.

00000b

2:0

Logical Stop Bit

Last logical bit that shall be mapped (bits are counted from least

significant bit (0) to most significant bit (7)).

R/W

000b

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