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LAN9252/ML bảng dữ liệu(PDF) 259 Page - Microchip Technology

tên linh kiện LAN9252/ML
Giải thích chi tiết về linh kiện  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
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LAN9252/ML bảng dữ liệu(HTML) 259 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 259
LAN9252
12.14.44 WATCHDOG STATUS PROCESS DATA REGISTER
Note:
Reading this register clears the Watchdog Process Data bit of the AL Event Request Register.
Note:
The Watchdog Status for the PDI can be read in the PDI Watchdog Status bit of the ESC DL Status Register.
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
12.14.45 WATCHDOG COUNTER PROCESS DATA REGISTER
12.14.46 WATCHDOG COUNTER PDI REGISTER
Offset:
0440h-0441h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:1
RESERVED
RO
RO
0000h
0
Watchdog Status of Process Data
(triggered by SyncManagers)
0:
Watchdog Process Data expired
1:
Watchdog Process Data is active or disabled
RO
RO
0b
Offset:
0442h
Size:
8 bits
Bits
Description
ECAT
Type
PDI
Type
Default
7:0
Watchdog Counter Process Data
Counting is stopped when FFh is reached. Counts if Process
Data Watchdog expires. This field is cleared if one of the Watch-
dog counters (0442h-0443h) is written.
R/WC
RO
00h
Offset:
0443h
Size:
8 bits
Bits
Description
ECAT
Type
PDI
Type
Default
7:0
Watchdog PDI Counter
Counting is stopped when FFh is reached. Counts if PDI Watch-
dog expires. This field is cleared if one of the Watchdog counters
(0442h-0443h) is written.
R/WC
RO
00h



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