PCM1723ESLASH2K datasheet(14/22 Pages) TI2

14 / 22 page

PCM1723

SBAS057A

www.ti.com

THEORY OF OPERATION

The delta-sigma section of the PCM1723 is based on a 5-

level amplitude quantizer and a 3rd-order noise shaper. This

section converts the oversampled input data to 5-level delta-

sigma format.

A block diagram of the 5-level delta-sigma modulator is

shown in Figure 16. This 5-level delta-sigma modulator has

the advantage of stability and clock jitter sensitivity over the

typical one-bit (2 level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modu-

lator and the internal 8X interpolation filter is 48fS for a

384fS system clock, and 64fS for a 256fS system clock. The

theoretical quantization noise performance of the 5-level

delta-sigma modulator is shown in Figure 17.

AC-3 APPLICATION CIRCUIT

A typical application for the PCM1723 is AC-3 5.1 channel

audio decoding and playback. This circuit uses the PCM1723

to develop the audio system clock from the 27MHz video

clock, with the SCKO pin used to drive the AC-3 decoder

and two PCM1720 units, the non-PLL version of the

PCM1723.

FIGURE 17. Quantization Noise Spectrum.

3rd ORDER

∆Σ MODULATOR

Frequency (kHz)

–20

–40

–60

–80

–100

–120

–140

–160

FIGURE 16. 5-Level

∆Σ Modulator Block Diagram.

Out

48f

S (384fS)

64f

S (256fS)

18-Bit

5-level Quantizer

–

Z–1

–

Z–1

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