LMH2191

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SNAS485D – JULY 2010 – REVISED MAY 2013

3.5 V ELECTRICAL CHARACTERISTICS

(1)

Unless otherwise specified, all limits are specified at TJ = 25°C, VBAT = 3.5V, CBAT = 1µF, COUT = 2.2 µF

(2), f

SCLK_IN = 26 MHz,

IOUT = 1mA, Boldface limits apply at the temperature extremes.

Symbol

Parameter

Condition

Min(3)

Typ(4)

Max(3)

Units

Supply Current(5)(6)

IDD

Supply Current

Active Mode SCLK_IN = 19.2 MHz;

1.65

both clock outputs toggling; CLOAD

1.4

mA

1.7

CLK1/2 = 0pF; IOUT = 0mA

Active Mode SCLK_IN = 19.2 MHz;

4.45

both clock outputs toggling; CLOAD for

3.7

mA

4.50

CLK1/2 = 33.5pF; IOUT = 0mA

Active Mode SCLK_IN = 26 MHz, both

2.15

clock outputs toggling, CLOAD for

1.9

mA

2.25

CLK1/2 = 0pF, IOUT=0mA

Active Mode SCLK_IN = 26 MHz, both

5.80

clock outputs toggling, CLOAD for

5

mA

5.95

CLK1/2 = 33.5 pF, IOUT=0mA

In shutdown. Input clock not active.

0.1

1

µA

CLK_REQ1/2=Low

In shutdown. Input clock toggling.

0.1

1

uA

CLK_REQ1/2=Low

CPD

Power Dissipation Capacitance

CLOAD for CLK1,2 = 0pF, Defined with

23.0

20

pF

per CLK output

respect to VOUT = 1.8V

24.0

Clock Outputs (CLK1/2) Figure 1, Figure 2

tPD_LH

Propagation Delay - Low to High

50% to 50%;

6.1

10.5

CLOAD = 33 pF; measured on CLK1

tPD_HL

Propagation Delay - High to Low

50% to 50%;

6.1

10.5

ns

CLOAD = 33 pF; measured on CLK1

tSKEW

Skew Between Outputs (Either

CLK1 to CLK2. 50% to 50%

1.5

3.1

Edge)

tRISE

Rise Time(7)

For CL between 33.5 pF - 50 pF, 20% to

2.1

3.7

5.9

80%; typical value based on 40 pF load

ns

tFALL

Fall Time(7)

For CL between 33.5 pF - 50 pF, 20% to

2

3.5

5

80%; typical value based on 40pF load

CLK_DC

Output Clock Duty Cycle

For CL between 33.5 pF - 50 pF

42

50

58

%

JitterRMS

Additive RMS period Jitter

fSCLK-IN= 26 MHz, BW =

CLK1

95

fs

100 Hz to 1MHz

CLK2

110

(1)

Electrical Table values apply only for factory testing (ATE) conditions at the temperature indicated. Factory testing conditions result in

very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables

under conditions of internal self-heating where TJ > TA.

(2)

CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(3)

Limits are 100% production tested at 25°C. Limits over temperature range are specified through correlations using statistical quality

control (SQC) method.

(4)

Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(5)

Supply current depends on switching frequency and load.

(6)

Positive current is current flowing into the device.

(7)

This parameter is specified by design and/or characterization and is not tested in production.

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