CS

SC

SO

t3

t2

t4

t1

t4

tr

tf

5

LM95071-Q1

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SNIS207 – DECEMBER 2018

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Logic Electrical Characteristics - Digital DC Characteristics (continued)

Unless otherwise noted, these specifications apply for VDD = 2.4 V to 5.5 V

(1).

PARAMETER

TEST CONDITIONS

MIN(2)

TYP(3)

MAX(2)

UNIT

Input Hysteresis

Voltage

VDD = 3 V to 3.6 V

TA = TJ = +25°C

0.4

V

TA = TJ = TMIN to TMAX

0.33

IIN(1)

Logical “1” Input

Current

VIN = VDD

TA = TJ = +25°C

0.005

µA

TA = TJ = TMIN to TMAX

3

IIN(0)

Logical “0” Input

Current

VIN = 0 V

TA = TJ = +25°C

−0.005

µA

TA = TJ = TMIN to TMAX

−3

CIN

All Digital Inputs

TA = TJ = +25°C

20

pF

VOH

High Level

Output Voltage

IOH = −400 µA, TA = TJ = TMIN to TMAX

2.25

V

VOL

Low Level

Output Voltage

IOL = +1.6 mA, TA = TJ = TMIN to TMAX

0.4

V

IO_TRI-

STATE

TRI-STATE

®Output

Leakage Current

VO = GND

VO = VDD, TA = TJ = TMIN to TMAX

−1

+1

µA

(1)

The of the LM95071-Q1 will operate properly over the VDD supply voltage range of 2.4V to 5.5V.

(2)

Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

(3)

Typicals are at TA = 25°C and represent most likely parametric norm.

6.7 Logic Electrical Characteristics - Serial Bus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for VDD = 2.4 V to 5.5 V

(1); C

L (load capacitance) on output lines = 100 pF

unless otherwise specified.

MIN(2)

TYP(3)

MAX(2)

UNIT

t1

SC (Clock) Period

TA = TJ = TMIN to TMAX

0.16

µs

TA = TJ = +25°C

DC

t2

CS Low to SC (Clock) High Set-Up Time

TA = TJ = TMIN to TMAX

100

ns

t3

CS Low to Data Out (SO) Delay

TA = TJ = TMIN to TMAX

70

ns

t4

SC (Clock) Low to Data Out (SO) Delay

TA = TJ = TMIN to TMAX

70

ns

t5

CS High to Data Out (SO) TRI-STATE

TA = TJ = TMIN to TMAX

200

ns

t6

SC (Clock) High to Data In (SI) Hold Time TA = TJ = TMIN to TMAX

50

ns

t7

Data In (SI) Set-Up Time to SC (Clock)

High

TA = TJ = TMIN to TMAX

30

ns

t8

SC (Clock) High to CS High Hold Time

TA = TJ = TMIN to TMAX

50

ns

6.8 Timing Diagrams

Figure 1. Data Output Timing Diagram