SLG51002 datasheet(9/37 Pages) RENESAS

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SLG51002

PMIC with High PSRR, Low Noise, Multi-Output LDOs

and Integrated Load Switches

Datasheet

Revision 3.11

25-Jul-2023

CFR0011-120-00

9 of 36

Characteristics

3.1

Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the

device. These are stress ratings only, so functional operation of the device at these or any other

conditions beyond those indicated in the operational sections of the specification are not implied.

Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Table 3: Absolute Maximum Ratings

Parameter

Description

Conditions

Min

Max

Unit

TSTG

Storage temperature

Non operational

-40

+150

°C

Junction temperature

-25

+125

°C

Ambient temperature

-40

+85

°C

VDD

Power supply voltage on VDD pin

-0.3

+6.0

VDDIO

Power supply voltage on VDDIO pin

-0.3

VDD

Power supply voltage on VIN1_2,

VIN3, VIN4, VIN5, VOUT1, VOUT2,

VOUT3, VOUT4, VOUT5 pins

-0.3

+6.0

Power supply voltage on VIN6, VIN7,

VIN8 pin

-0.3

+1.8

Voltage on VOUT6, VOUT7, VOUT8

-0.3

+1.65

VPIN

Voltage on low voltage pins

GPIO5 and GPI6

-0.3

+1.98

Voltage on high voltage pins

GPIO1 to GPIO4

-0.3

VDDIO + 0.3

-0.3

VDD + 0.3

Voltage on LDO output pins

-0.3

VIN + 0.3

ESD

ESD Protection (Human Body Model)

2000

ESD Protection (Charged Device

Model)

500

IMAX_LDO_LV

Maximum Average or DC Current

through VIN6, VIN7, VIN8 or VOUT6,

VOUT7, VOUT8 Pins

TJ = 100 °C

1.3

TJ = 110 °C

0.938

3.1.1

Guidelines for Reliable Operation

● Low Voltage Pins (GPIO5 and GPI6): take care that the low voltage pins do not exceed their Abs.

Max. ratings, even briefly. Transients both positive (above max) and negative (below min) can cause

EOS (Electrical Overstress) damage.

● Power sequencing: CS should be held low before VDD is powered up. CS pin should also be pulled

low before VDD falls out of operating range. VIN supplies for LDO_HV, LDO_HC and LDO_LV

channels can be safely biased even if VDD is not present. VIN supplies should be powered up before

enabling their respective LDO channels. Low voltage pins (GPIO5 and GPI6) configured as inputs are

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