SLG47115 datasheet(82/255 Pages) RENESAS

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R19DS0118EU0119 Rev.1.19

Page 82

Sep 16, 2024

SLG47115 Datasheet

10. Connection Matrix

10.1 Connection Matrix Structure

The Connection Matrix in the SLG47115 is used to create the internal routing for internal functional macrocells of

the device once it is programmed. The registers are programmed from the one-time NVM cell during Test mode

operation. The output of each functional macrocell within the SLG47115 has a specific digital bit code assigned to

it, that is either set to active “HIGH”, or inactive “LOW”, based on the design that is created. Once the 2048

The Connection matrix has 64 inputs and 96 outputs. Each of the 64 inputs to the Connection matrix is hard-wired

to the digital output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital

resources, such as VDD and GND. The input to a digital macrocell uses a 6-bit register to select one of these 64

input lines.

For a complete list of the SLG47115’s register table, see Section 23. Register Definitions.

Figure 52. Connection Matrix

Figure 53. Connection Matrix Example

GND

LUT2_0/DFF OUT

LUT2_1/DFF OUT

LUT2_2/DFF OUT

Matrix input signal

functions

TSD_FAULT

VDD

Function

Registers

Diff_Amp_Integrator_En

registers [569:564]

GPIO0

digital output

registers [5:0]

GPIO0

digital output OE

registers [11:6]

GPIO1

digital output

registers [17:12]

Matrix inputs

Matrix outputs

LUT

GPIO4

GPIO0

GPIO1

Function

GPIO0

GPIO1

Connection Matrix

LUT

GPIO4

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