SN74ACT2228 datasheet(11/15 Pages) TI

11 / 15 page

SN74ACT2226, SN74ACT2228

DUAL 64

× 1, DUAL 256 × 1

CLOCKED FIRST-IN, FIRST-OUT MEMORIES

SCAS219C – JUNE 1992 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

SINGLE FIFO SUPPLY CURRENT

CLOCK FREQUENCY

fclock – Clock Frequency – MHz

fI = 1/2 fclock

TA = 75°C

CL = 0 pF

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

Figure 5

calculating power dissipation

Data for Figure 5 is taken with one FIFO active and one FIFO idle on the device. The active FIFO has both writes

and reads enabled with its read clock (RDCLK) and write clock (WRTCLK) operating at the rate specified by

fclock. The data input rate and data output rate are half the fclock rate, and the data output is disconnected. A

close approximation of the total device power can be found by using Figure 5, determining the capacitive load

on the data output and determining the number of SN74ACT2226/2228 inputs driven by TTL high levels.

With ICC(f) taken from Figure 5, the maximum power dissipation (PT) of one FIFO on the SN74ACT2226 or

SN74ACT2228 can be calculated by:

PT = VCC × [ICC(f) + (N × ∆ICC × dc)] + (CL × VCC2 × fo)

where:

= number of inputs driven by TTL levels

∆ICC = increase in power-supply current for each input at a TTL high level

= duty cycle of inputs at a TTL high level of 3.4 V

= output capacitive load

= switching frequency of an output

SN74ACT2228 bảng dữ liệu(PDF) 11 Page - Texas Instruments