SC4525CEVB datasheet(16/22 Pages) SEMTECH

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SC4525C

Applications Information (Cont.)

The total power loss of the SC4525C is therefore

TOTAL = PC + PSW + PBST = PQ

The temperature rise of the SC4525C is the product of the

total power dissipation (see previous equation) and q

(36oC/W), which is the thermal impedance from junction

to ambient for the SOIC-8 EDP package.

It is not recommended to operate the SC4525C above

25oC junction temperature.

PCB Layout Considerations

In a step-down switching regulator, the input bypass

capacitor, the main power switch and the freewheeling

diode carry pulse current (Figure 9). For jitter-free

operation,thesizeoftheloopformedbythesecomponents

should be minimized. Since the power switch is already

integrated within the SC4525C, connecting the anode of

the freewheeling diode close to the negative terminal of

the input bypass capacitor minimizes size of the switched

current loop. The input bypass capacitor should be placed

close to the IN pin. Shortening the traces of the SW and

BST nodes reduces the parasitic trace inductance at these

nodes. This not only reduces EMI but also decreases

switching voltage spikes at these nodes.

The exposed pad should be soldered to a large ground

plane as the ground copper acts as a heat sink for the

device. To ensure proper adhesion to the ground plane,

avoid using vias directly under the device.

OUT

Figure 9 — Pulse Current Loop

NOTE: Heavy lines indicate the critical pulse current loop. The stray

inductance of this loop should be minimized.

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