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–2

–3

–4

–5

R

LOAD (kΩ)

0.001

0.01

1

0.1

100

10

1000

Source

Sink

2

1.5

1

0.5

0

Digital Input Code

0000

H

2000

H

4000

H

6000

H

8000

H

A000

H

C000

H

E000

H

FFFF

H

No Load

All DACs

One DAC

Large−Signal Settling Time: 1V/div

Small−Signal Settling Time:

2LSB/div

+5V

LDAC

0

Time (2

µs/div)

+5V

LDAC

0

Large−Signal Settling Time: 1V/div

Small−Signal Settling Time: 2LSB/div

Time (2

µs/div)

THEORY OF OPERATION

DAC7634

SBAS134B – JULY 2004 – REVISED DECEMBER 2005

TYPICAL PERFORMANCE CURVES: V

SS = –5 V (continued)

At T

A = 25°C, VDD = VCC = 5 V, VREFH = 2.5 V, VREFL = 0 V, representative unit, unless otherwise specified.

VOUT vs RLOAD

POSITIVE SUPPLY CURRENT

vs DIGITAL INPUT CODE

Figure 44.

Figure 45.

OUTPUT VOLTAGE vs SETTLING TIME

OUTPUT VOLTAGE vs SETTLING TIME

(–2.5 V TO 2.5 V)

(2.5 V TO –2.5 V)

Figure 46.

Figure 47.

The DAC7634 is a quad voltage output, 16-bit

The digital input is a 24-bit serial word that contains a

digital-to-analog converter (DAC). The architecture is

2-bit address code for selecting one of four DACs, a

an R-2R ladder configuration with the three MSBs

quick load bit, five unused bits, and the 16-bit DAC

segmented, followed by an operational amplifier that

code (MSB first). The converters can be powered

serves as a buffer. Each DAC has its own R-2R

from either a single 5-V supply or a dual ±5-V supply.

ladder

network,

segmented

MSBs,

and

output

The device offers a reset function which immediately

operational amplifier, as shown in Figure 48. The

sets all DAC output voltages and DAC registers to

minimum voltage output (zero-scale) and maximum

mid-scale code 8000H or to zero-scale, code 0000H.

voltage output (full-scale) are set by the external

See Figure 49 and Figure 50 for the basic operation

voltage references (VREFL and VREFH, respectively).

of the DAC7634.

16