CC1070-RTY1 datasheet(31/57 Pages) TI2

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CC1070

SWRS043A

Page 31 of 54

End of calibration

Read STATUS register and wait until

CAL_COMPLETE=1

Start calibration

Write MAIN register = 91h or D1h:

F_REG=0 (or 1), PD_MODE=1,

FS_PD=0, CORE_PD=0, BIAS_PD=0,

RESET_N=1

Write FREQ_A, FREQ_B, VCO,

CLOCK_A and CLOCK_B registers.

PLL_BW = 146 + 16log

2(fref/7.126)

Write CALIBRATE register = BCh

Start calibration

Calibrate TX frequency register A

(MAIN = 91h) or B (MAIN = D1h)

ref is the reference frequency (in

MHz)

Read STATUS register and wait until

LOCK_CONTINUOUS=1

Wait for T ≥ 100 us

Yes

Calibration OK?

End of calibration

Read STATUS register and wait until

CAL_COMPLETE=1

Start calibration

Write MAIN register = 91h or D1h:

F_REG=0 (or 1), PD_MODE=1,

FS_PD=0, CORE_PD=0, BIAS_PD=0,

RESET_N=1

Write FREQ_A, FREQ_B, VCO,

CLOCK_A and CLOCK_B registers.

PLL_BW = 146 + 16log

2(fref/7.126)

Write CALIBRATE register = BCh

Start calibration

Calibrate TX frequency register A

(MAIN = 91h) or B (MAIN = D1h)

ref is the reference frequency (in

MHz)

Read STATUS register and wait until

LOCK_CONTINUOUS=1

Wait for T ≥ 100 us

Yes

Calibration OK?

Figure 17. Calibration algorithm

14.3 PLL Turn-on Time versus Loop Filter Bandwidth

If calibration has been performed the PLL

turn-on time is the time needed for the

PLL to lock to the desired frequency when

going from power down mode (with the

crystal oscillator running) to TX mode. The

PLL turn-on time depends on the PLL loop

filter bandwidth. Table 19 gives the PLL

turn-on time for different PLL loop filter

bandwidths.

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