PASS

ELEMENT

VREF

NOISE

SUPPRESSION

VOLTAGE

CONTROL

VIN_C

VIN_B

REGULATED

OUTPUT

LM3537

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SNVS634B – JUNE 2011 – REVISED MAY 2013

The power input voltage applied between VIN_C and GND should be at least 0.3V above the output voltage of the

regulators. The bias input voltage applied between VIN_B and GND should be equal to VIN_A, and at least 0.3V

above the output voltage of the regulators.

VIN_B supplies internal circuitry. VIN_C, the power input voltage, is regulated to the fixed output voltage.

Figure 6. LDO Block Diagram

I

2C-Compatible Interface

STOP AND START CONDITIONS

The LM3537 is controlled via an I2C-compatible interface. START and STOP ) conditions classify the beginning

and the end of the I2C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL

is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C

master always generates START and STOP conditions. The I2C bus is considered busy after a START condition

and free after a STOP condition. During data transmission, the I2C master can generate repeated START

conditions. A START and a repeated START conditions are equivalent function-wise. The data on SDA must be

stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed

when SCL is LOW.

Figure 7. Start and Stop Sequences

I2C-COMPATIBLE CHIP ADDRESS

The chip address for the LM3537 is 0111000 (38h). After the START condition, the I2C master sends the 7-bit

chip address followed by a read or write bit (R/W). R/W= 0 indicates a WRITE and R/W = 1 indicates a READ.

The second byte following the chip address selects the register address to which the data will be written. The

third byte contains the data for the selected register.

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