LM25115A

SNVS501B – FEBRUARY 2007 – REVISED APRIL 2013

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Vphase=10V

CH1 = CO, 5V/Div

CH2 = COMP, 5/Div

CH3 = Iout, 10A/Div

CH4 = SSPR Switch Signal, 4V/Div

Horizontal Resolution= 20 µs/Div

Figure 24. SSPR Short Circuit Transient (No-Load to Short-Circuit)

Negative Current Limit

Under certain conditions synchronous buck regulators are capable of sinking current from the output capacitors.

This energy is stored in the inductor and returned to the input source. The LM25115A detects this current

reversal by detecting a negative voltage being developed across the current sense resistor. The intent of this

negative current comparator is to protect the low-side MOSFET from excessive currents. Excessive negative

current can also lead to a large positive voltage spike on the HS pin at the turn-off of the low-side MOSFET. This

voltage spike may damage the chip if its magnitude exceeds the maximum voltage rating of the part. The

negative current comparator threshold is sufficiently negative to allow inductor current to reverse at no load or

light load conditions. It is not intended to support discontinuous conduction mode with diode emulation by the

low-side MOSFET. The negative current comparator shown in Figure 21 monitors the CV signal and compares

this signal to a fixed 1V threshold. This corresponds to a negative VCL voltage between CS and VOUT of -17mV.

The negative current limit comparator turns off the low-side MOSFET for the remainder of the cycle when the VCL

input falls below this threshold.

Gate Driver Outputs (HO & LO)

The LM25115A provides two gate driver outputs, the floating high-side gate driver HO and the synchronous

rectifier low-side driver LO. The low-side driver is powered directly by the VCC regulator. The high-side gate

driver is powered from a bootstrap capacitor connected between HB and HS. An external diode connected

between VCC and HB charges the bootstrap capacitor when the HS is low. When the high-side MOSFET is

turned on, HB rises with HS to a peak voltage equal to VCC + VHS - VD where VD is the forward drop of the

external bootstrap diode. Both output drivers have adaptive dead-time control to avoid shoot through currents.

The adaptive dead-time control circuit monitors the state of each driver to ensure that one MOSFET is turned off

before the other is turned on. The HB and VCC capacitors should be placed close to the pins of the LM25115A

to minimize voltage transients due to parasitic inductances and the high peak output currents of the drivers. The

recommended range of the HB capacitor is 0.047µF to 0.22µF.

Both drivers are controlled by the PWM logic signal from the PWM latch. When the phase signal is low, the

outputs are held in the reset state with the low-side MOSFET on and the high-side MOSFET off. When the phase

signal switches to the high state, the PWM latch reset signal is de-asserted. The high-side MOSFET remains off

until the PWM latch is set by the PWM comparator (CRMIX > CV as shown in Figure 19). When the PWM latch

is set, the LO driver turns off the low-side MOSFET and the HO driver turns on the high-side MOSFET. The high-

side pulse is terminated when the phase signal falls and SYNC input comparator resets the PWM latch.

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