CLC006

8

4

3

1

5

2

VCC

6

7

R2

R1

R2

R1

-

+

0.1 PF

0.1 PF

VEE

VCC

VEE

Z0

Z0

VTT

VTT

ECL Output

To next

stage

VIN+

VIN-

VEE

VCC

CLC006

SNLS015G – AUGUST 1998 – REVISED APRIL 2013

www.ti.com

Operation

INPUT INTERFACING

The CLC006 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be

input. Transmission lines supplying input signals must be properly terminated close to the CLC006. Either A.C. or

D.C. coupling as in Figure 4 or Figure 5 may be used. Figure 4, Figure 6 and Figure 7 show how Thevenin-

equivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode

voltage range is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias should be kept within

the specified common-mode range. For an 800 mVP-P input signal, typical input bias levels range from 1.2V to

2.1V below the positive supply.

Load Type

Resistor to VCC (R1)

Resistor to VEE (R2)

ECL, 50

Ω, 5V, VT=2V

82.5

Ω

124

Ω

ECL, 50

Ω, 5.2V, VT=2V

80.6

Ω

133

Ω

ECL, 75

Ω, 5V, VT=2V

124

Ω

187

Ω

ECL, 75

Ω, 5.2V, VT=2V

121

Ω

196

Ω

800 mVP-P, 50Ω, 5V, VT=1.6V

75.0

Ω

154

Ω

800 mVP-P, 75Ω, 5V, VT=1.6V

110

Ω

232

Ω

800 mVP-P, 2.2KΩ, 5Ω, VT=1.6V

3240

Ω

6810

Ω

Figure 3. Input Stage

Figure 4. AC Coupled Input

4

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