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74ACT11238DR bảng dữ liệu(PDF) 1 Page - Texas Instruments

tên linh kiện 74ACT11238DR
Giải thích chi tiết về linh kiện  3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
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74ACT11238DR bảng dữ liệu(HTML) 1 Page - Texas Instruments

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74ACT11238
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Copyright
© 1993, Texas Instruments Incorporated
2–1
• Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
• Noninverting Version of ′ACT11138
• Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V
CC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-
mm Process
• 500-mA Typical Latch-Up Immunity
at 125
°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The 74ACT11238 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory. This means that the effective system delay introduced by the decoder
is negligible.
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
The 74ACT11238 is characterized for operation from – 40
°C to 85°C.
FUNCTION TABLE
ENABLE
SELECT
OUTPUTS
INPUTS
INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
L
L
L
L
L
L
L
L
X
XH
X
XX
L
LL
LL
LL
L
L
XX
X
XX
L
LL
LL
LL
L
H
LL
L
LL
H
LL
LL
LL
L
H
LL
L
LH
L
H
L
LL
LL
L
H
LL
L
HL
L
L
H
LL
LL
L
H
LL
L
HH
L
LL
H
L
LL
L
H
LL
H
LL
L
LL
L
H
LL
L
H
LL
H
LH
L
LL
LL
H
L
L
H
LL
H
HL
L
LL
LL
L
H
L
H
L
L
H
H
H
L
L
L
L
L
L
L
H
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
Y0
A
B
C
VCC
G1
G2A
G2B
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.


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