ADS5271 datasheet(31/42 Pages) TI2

31 / 42 page

ADS5287

www.ti.com

SBAS428D – JANUARY 2008 – REVISED JUNE 2012

APPLICATION INFORMATION

The ADC output goes to a serializer that operates

THEORY OF OPERATION

from a 12x clock generated by the PLL. The 12 data

bits from each channel are serialized and sent LSB

The ADS5287 is an 8-channel, high-speed, CMOS

first. In addition to serializing the data, the serializer

ADC. Two zeroes are appended on the LSB side to

also generates a 1x clock and a 6x clock. These

the 10 bits given out by each channel. The resulting

clocks are generated in the same way the serialized

12 bits are serialized and sent out on a single pair of

data are generated, so these clocks maintain perfect

pins in LVDS format. All eight channels of the

synchronization with the data. The data and clock

ADS5287 operate from a single clock (ADCLK). The

outputs of the serializer are buffered externally using

sampling clocks for each of the eight channels are

LVDS buffers. Using LVDS buffers to transmit data

generated from the input clock using a carefully

externally has multiple advantages, such as a

matched clock buffer tree. The 12x clock required for

reduced number of output pins (saving routing space

the serializer is generated internally from ADCLK

on the board), reduced power consumption, and

using a phase-locked loop (PLL). A 6x and a 1x clock

reduced effects of digital noise coupling to the analog

are also output in LVDS format, along with the data,

circuit inside the ADS5287.

to enable easy data capture. The ADS5287 operates

from internally-generated reference voltages that are

The ADS5287 operates from two sets of supplies and

trimmed to achieve a high level of accuracy. Trimmed

grounds. The analog supply and ground set is

references

improve

the

gain

matching

across

identified as AVDD and AVSS, while the digital set is

devices, and provide the option to operate the

identified by LVDD and LVSS.

devices without having to externally drive and route

reference lines. The nominal values of REFT and

ANALOG INPUT

REFB

are

2.5V

and

0.5V,

respectively.

The

references are internally scaled down differentially by

The analog input consists of a switched-capacitor

a factor of 2. This scaling results in a differential input

based, differential sample-and-hold architecture. This

of –1V to correspond to the zero code of the ADC,

differential

topology

results

very

good

and a differential input of +1V to correspond to the

performance, even for high input frequencies at high

full-scale code (1023 LSB). VCM (the common-mode

sampling rates. The INN and INP pins must be

voltage of REFT and REFB) is also made available

externally biased around a common-mode voltage of

externally through a pin, and is nominally 1.5V.

1.5V, available on VCM. For a full-scale differential

input, each input pin (INN and INP) must swing

The ADC employs a pipelined converter architecture

symmetrically between VCM + 0.5V and VCM – 0.5V,

that consists of a combination of multi-bit and single-

resulting in a 2VPP differential input swing. The

bit internal stages. Each stage feeds its data into the

maximum input peak-to-peak differential swing is

digital

error

correction

logic,

ensuring

excellent

determined to be the difference between the internal

differential linearity and no missing codes at the 10-

reference voltages REFT (2.5V nominal) and REFB

bit level.

(0.5V nominal). Figure 31 illustrates the model of the

input driving circuit.

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