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ADC14DC080 bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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ADC14DC080 bảng dữ liệu(HTML) 2 Page - Texas Instruments |
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2 / 26 page  VA VA VA VA AGND AGND VA AGND ADC14DC080 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 VRPA VDR 32 31 45 44 43 42 41 40 39 38 37 35 34 33 36 VINA- VINA+ AGND AGND AGND VA AGND VINB- VCMOA VRNA VCMOB VRNB VRPB DRGND * Exposed Pad VINB+ DB8 DB9 DB10 DB13 (MSB) DB12 DB11 DRDY DA0 (LSB) DA1 DA2 DA5 DA4 DA3 ADC14DC080 SNAS463B – SEPTEMBER 2008 – REVISED APRIL 2013 www.ti.com Connection Diagram Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit Description ANALOG I/O 3 VINA+ 13 VINB+ Differential analog input pins. The differential full-scale input signal level is 2VP-P with each input pin signal centered on a common mode 2 VINA- voltage, VCM. 14 VINB- 5 VRPA 11 VRPB 7 VCMOA 9 VCMOB These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor placed very close to the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor should be placed between VRP and VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. VRP and VRN should not be loaded. VCMO may be loaded to 1mA for 6 VRNA use as a temperature stable 1.5V reference. 10 VRNB It is recommended to use VCMO to provide the common mode voltage, VCM for the differential analog inputs. 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC14DC080 |
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