ADC12DS080

3x 0.1 PF

5x 0.1 PF

59

+

10 PF

+3.3V

0.1 PF

20

20

0.1 PF

1

V

IN_B

VINA-

VINA+

13

14

50

5

6

0.1 PF

20

20

0.1 PF

1

V

IN_A

VINB-

VINB+

2

3

OF/DCS

CLK

Crystal Oscillator

18

19

57

20

27

PD_A

47

29

45

To capture device (ASIC or FPGA).

Note, all signal pairs should be routed with

100 ohm differential impedance, and should

be terminated with a 100 ohm resistor near

the input of the capture device.

18 pF

18 pF

9

11

10

0.1 PF

ADT1-1WT

0.1 PF

VRPA

VRNA

VCMOA

0.1 PF

0.1 PF

1 PF

0.1 PF

0.1 PF

50

7

0.1 PF

0.1 PF

1 PF

0.1 PF

0.1 PF

ADT1-1WT

VCMOB

VRPB

VRNB

VREF

0.1 PF

PD_B

TEST

WAM

SPI_EN

56

SPI_EN

These control pins are

ignored when SPI_EN is high

LVDS_Bias

3.6k

FRAME-

SD0_B-

SD0_B+

SD1_B-

SD1_B+

SD0_A-

SD0_A+

SD1_A-

SD1_A+

FRAME+

OUTCLK-

OUTCLK+

44

43

42

38

37

36

35

34

33

32

31

52

SCLK

SDI

SDO

53

54

55

SCSb

SPI Interface

+3.0V

ADC12DS080

www.ti.com

SNAS443A – MARCH 2008 – REVISED MARCH 2013

Figure 23. Application Circuit

Serial Control Interface

The ADC12DS080 has a serial interface that allows access to the control registers. The serial interface is a

generic 4-wire synchronous interface that is compatible with SPI type interfaces that are used on many

microcontrollers and DSP controllers.

The ADC's input clock must be running for the Serial Control Interface to operate. It is enabled when the SPI_EN

(pin 56) signal is asserted high. In this case the direct control pins (OF/DCS, PD_A, PD_B, DLC, WAM, TEST)

have no effect. When this signal is deasserted, the SPI interface is disabled and the direct control pins are

enabled.

Each serial interface access cycle is exactly 16 bits long. Figure 24 shows the access protocol used by this

interface. Each signal's function is described below. The Read Timing is shown in Figure 25, while the Write

Timing is shown in Figure 26

Copyright © 2008–2013, Texas Instruments Incorporated

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