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POWER MANAGEMENT

SC2608B

Synchronous Buck Converter

Synchronous Buck Converter

Synchronous Buck Converter

Synchronous Buck Converter

Synchronous Buck Converter

The output voltage of the synchronous converter is set

and controlled by the output of the error amplifier. The

inverting input of the error amplifier receives its voltage

from the SENSE pin. The non-inverting input of the error

amplifier is connected to an internal 0.8V reference. The

error amplifier output is connected to the compensation

pin. The error amplifier generates a current proportional

to (0.8V-Vsense), which is the COMP pin output current

(Transconductance ~ 7mS).

The voltage on the COMP

pin is the integral of the error amplifier current. The COMP

voltage is the non-inverting input of the PWM compara-

tor and controls the duty cycle of the MOSFET drivers.

The compensation network controls the stability and tran-

sient response of the regulator. The larger capacitor,

the slower COMP voltage changes, and slower the duty

cycle changes.

The non-inverting input voltage of the PWM comparator

is the triangular ramp signal generated from the oscilla-

tor. The peak-to-peak voltage of the ramp is 1V, this is a

parameter used in control loop calculation. When the

oscillator ramp signal rises above the COMP voltage, the

comparator output goes high and the PWM latch is re-

set. This pulls DH low, turning off the high-side MOSFET.

After a short delay (dead time), DL is pulled high, turning

on the low-side MOSFET. The oscillator also produces a

set pulse for the PWM latch to turn off the low-side

MOSFET, After a delay time, DH is pulled high to turn on

the high-side MOSFET. The delay time is determined by a

monostable on the chip.

The triangle wave minimum is about 0.8V, and the maxi-

mum is about 1.8V. Thus, if Vcomp = 0.7V, high side duty

cycle is the minimum (~0%) , but if Vcomp is 1.8V, duty

cycle is at maximum ( ~90%).The internal oscillator uses an

on-chip capacitor and trimmed precision current sources

to set the oscillation frequency to 250kHz. Figure 1 shows

a 2.5V output converter. If the Vout <2.5V, then the SENSE

voltage < 0.8V. In this case the error amplifier will be sourc-

ing current into the COMP pin so that COMP voltage and

duty cycle will gradually increase.If Vout > 2.5V, the error

amplifier will sink current and reduce the COMP voltage, so

that duty cycle will decrease.The circuit will be in steady

state when Vout =2.5V , Vsense = 0.8V, Icomp = 0. The

COMP voltage and duty cycle depend on Vin.

U

U

U

U

Under V

nder V

nder V

nder V

nder Voltage Lock

oltage Lock

oltage Lock

oltage Lock

oltage Lockout

out

out

out

out

The under voltage lockout circuit of the SC2608B as-

sures that both high-side and low-side MOSFET driver

outputs remain in the off state whenever the supply volt-

age drops below the set threshold. Lockout occurs if V

CC

falls below 3.6V typ.

Soft Start

Soft Start

Soft Start

Soft Start

Soft Start

The SC2608B provides a soft start function to prevent large

inrush currents upon power-up or hiccup retry. If both COMP

and SENSE pins are low (<300mV), the device enters soft

start mode, and the compensation capacitor is slowly

charged by an internal 4uA current source. When the COMP

pin reaches 300mV, the low side FET is switched on in order

to refresh the bootstrap capacitor, and begin PWM from a

known state. As the COMP pin rises above 800mV, PWM

begins at minimum duty cycle.

COMP continues to charge, slowly sweeping the device

through the duty cycle range until FB reaches the regulation

point of 800mV. Once FB reaches the regulation point, the

soft start current is switched off, and the strong error amp

is enabled, providing a glitch-free entrance into closed loop

operation. The overcurrent comparator is still active during

soft start mode, and will override soft start in the event

that an overcurrent is detected, such as startup into a

dead short.

R

R

R

R

R

DS(ON)

DS(ON)

DS(ON)

DS(ON)

Current Limiting

Current Limiting

Current Limiting

Current Limiting

In case of a short circuit or overload, the low-side (LS) FET

will conduct large currents. To protect the regulator in this

situation, the controller will shut down the regulator and

begin a soft start cycle later. While the LS driver is on,the

Phase voltage is compared to the OCP trip voltage. If the

phase voltage is lower than OCP trip voltage, an over cur-

rent condition is detected. The low-side R

mented at end of each LS-FET turn-on duration. The mini-

mum turn-on time of the LS-FET is set to be 400nS. This

will ensure the sampled signal is noise free by giving enough

time for the switching noise to die down.

Theory of Operation

OCP Hiccup

OCP Hiccup

OCP Hiccup

OCP Hiccup

OCP Hiccup

In the event that an overcurrent is detected, the SC2608B

latches the fault and begins a hiccup cycle. Switching is

immediately stopped, and the drivers are set to a tristate

condition (Both DH and DL are low). COMP is slowly

discharged to 300mV with an internal 4uA current source,

providing a long cooldown time to keep power dissipation

low in the event of a continuous dead short. Once COMP

and SENSE both fall below the 300mV threshold, the part

re-enables the 4uA soft start current , and the device begins

a normal startup cycle again.