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DDC232CK bảng dữ liệu(PDF) 16 Page - Texas Instruments

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DDC232CK bảng dữ liệu(HTML) 16 Page - Texas Instruments

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Integrate A
Integrate B
Integrate B
Integrate A
m/r/az B
m/r/az A
m/r/az B
CONV
State
Integration
Status
m/r/az
Status
mbsy
DVALID
tMRAZ
tCMDR
t = 0
Power−Up
Side B
Data
Side A
Data
Side B
Data
DDC232
SBAS331D – AUGUST 2004 – REVISED APRIL 2010
www.ti.com
TIMING EXAMPLES
top signal is CONV and is supplied by the user. The
Continuous Mode
next line indicates the current state in the state
diagram. The following two traces show when
A few timing diagrams help illustrate the operation of
integrations and measurement cycles are underway.
the
integrate/measure
state
machine.
These
The internal signal mbsy is shown next. Finally,
diagrams are shown in Figure 11 through Figure 16.
DVALID is given. As described in the data sheet,
Table 9 gives generalized timing specifications in
DVALID goes active low when data are ready to be
units of CLK periods for Clk_4x = 0. If Clk_4x = 1,
retrieved from the DDC232. It stays low until DCLK is
these values increase by a factor of 4 because of the
taken high and then back low by the user. The text
internal clock divider. Values (in ms) for Table 9 can
below the DVALID pulse indicates the side of the
be easily found for a given CLK.
data available to be read and arrows help match the
Figure 11 shows a few integration cycles beginning
data to the corresponding integration.
with initial power-up for a Cont mode example. The
Figure 11. Continuous Mode Timing
Table 9. Timing Specifications Generalized in CLK Periods
VALUE
(CLK Periods with Clk_4x = 0)
SYMBOL
DESCRIPTION
DDC232C
DDC232CK
tMRAZ
Continuous mode, m/r/az cycle
1552 ± 2
1612 ± 2
tCMDR
Continuous mode, data ready
1382 ± 2
1382 ± 2
16
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Product Folder Link(s): DDC232



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