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DDC232C bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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DDC232C bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 35 page ![]() Serial Interface DVALID DCLK DOUT DIN Configuration and Control IN2 IN1 DGND AGND IN4 IN3 IN30 IN29 DS ADC IN32 IN31 CLK CONV DIN_CFG CLK_CFG RESET Dual Switched Integrator Dual Switched Integrator Dual Switched Integrator Dual Switched Integrator Dual Switched Integrator Dual Switched Integrator Dual Switched Integrator Dual Switched Integrator VREF DVDD AVDD 0.1 F m 0.1 F m 0.1 F m DS ADC DS ADC DS ADC DDC232 www.ti.com SBAS331D – AUGUST 2004 – REVISED APRIL 2010 THEORY OF OPERATION GENERAL DESCRIPTION converters via multiplexers. With the DDC232 in the The block diagram of the DDC232 is shown in continuous integration mode, the output of the Figure 2. The device contains 32 identical input integrators from one side of the inputs will be digitized channels that perform the function of while the other 32 integrators are in the integration current-to-voltage integration followed by a mode. This integration and A/D conversion process is multiplexed A/D conversion. Each input has two controlled by the system clock, CLK. The results from integrators so that the current-to-voltage integration side A and side B of each signal input are stored in a can be continuous in time. The output of the 64 serial output shift register. The DVALID output goes integrators are switched to 16 delta-sigma ( ∆Σ) low when the shift register contains valid data. Figure 2. DDC232 Block Diagram Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): DDC232 |
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