DAC813 datasheet(7/17 Pages) TI2

7 / 17 page

DAC813

gain error. The reference output may be used to drive

external loads, sourcing at least 5mA. This current should be

constant, otherwise the gain of the converter will vary.

POWER SUPPLY SENSITIVITY

Power supply sensitivity is a measure of the effect of a

power supply change on the D/A converter output. It is

defined as a ppm of FSR output change per percent of

change in either +VCC or –VCC about the nominal voltages

expressed in ppm of FSR/%. The first performance curve on

page 5 shows typical power supply rejection versus power

supply ripple frequency.

OPERATION

DAC813 is a complete single IC chip 12-bit D/A converter.

The chip contains a 12-bit D/A converter, voltage reference,

output amplifier, and microcomputer-compatible input logic

as shown in Figure 1.

INTERFACE LOGIC

Input latches hold data temporarily while a complete 12-bit

word is assembled before loading into the D/A latch. This

double-buffered organization prevents the generation of spu-

rious analog output values. Each latch is independently

addressable.

All latches are level-triggered. Data present when the con-

trol signals are logic “0” will enter the latch. When any one

of the control signals returns to logic “1”, the data is latched.

A truth table for the control signals is presented in Table II.

FIGURE 1. DAC813 Block Diagram.

TABLE II. DAC813 Interface Logic Truth Table.

LLSB

LMSB LDAC RESET

OPERATION

No operation

XXXX

D/A latch set to 800HEX

0101

Enables 4 MSBs input latch

0011

Enables 8 LSBs input latch

0110

Loads D/A latch from input latches

0000

Makes all latches transparent

“X” = Don’t Care

CAUTION: DAC813 was designed to use WR as the fast

strobe. WR has a much faster logic path than EN

X (or

LDAC). Therefore, if one permanently wires WR to DCOM

and uses only EN

X to strobe data into the latches, the

DATA HOLD time will be long, approximately 15ns to

30ns, and this time will vary considerably in this range

from unit to unit. DATA HOLD time using WR is 5ns max.

LOGIC INPUT COMPATIBILITY

The DAC813 digital inputs are TTL, 5V CMOS compat-

ible over the operating range of +V

CC. The input switching

threshold remains at the TTL threshold over the supply

range. An equivalent circuit of a digital input is shown in

Figure 2.

The logic input current over temperature is low enough to

permit driving the DAC813 directly from the outputs of 5V

CMOS devices.

Open DATA input lines will float to 7V or more. Although

this will not harm the DAC813, current spikes will occur in

the input lines when a logic 0 is asserted and, in addition,

LSB

25k

Ω

25k

Ω

24.9k

Ω

BPO

20V

Range

OUT

12-Bit D/A Converter

12-Bit D/A Latch

4-Bit Latch

8-Bit Latch

MSB

D11

DCOM

0–800µA

49.5k

Ω

+10V

Reference

–V

ACOM

REF OUT

REF IN

LMSB

LLSB

LDAC

Reset

20V

Range

(1)

NOTE: (1) V

L must be connected to +VCC.

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