12

DAC7616

SBAS186

CS(1)

CLK(1)

LDAC

RESET

SERIAL SHIFT REGISTER

H(2)

X(3)

H

H

No Change

L(4)

L

H

H

No Change

L

↑(5)

H

H

Advanced One Bit

↑

L

H

H

Advanced One Bit

H(6)

XL(7)

H

No Change

H(6)

XH

L(8)

No Change

NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =

Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH

value is suggested in order to avoid a “false clock” from advancing the shift

register and changing the shift register. (7) If data is clocked into the serial

register while LDAC is LOW, the selected DAC register will change as the shift

register bits “flow” through A1 and A0. This will corrupt the data in each DAC

register that has been erroneously selected. (8) RESET LOW causes no

change in the contents of the serial shift register.

FIGURE 3. Suggested Power and Ground Connections for a DAC7616 Sharing a +3V Supply with a Digital System.

TABLE III. Serial Shift Register Truth Table.

If both CS and CLK are used, then CS should rise only when

CLK is HIGH. If not, then either CS or CLK can be used to

operate the shift register. See Table III for more information.

+3V

Power Supply

Optional

Digital Circuits

DAC7616

Other

Analog

Components

+3V

100

µF

1

µF to

10

µF

Ground

+3V

Ground

V

DD

AGND

0.1

µF

++

Digital Input Coding

The DAC7616 input data is in Straight Binary format. The

output voltage is given by the following equation:

where N is the digital input code (in decimal). This equation

does not include the effects of offset (zero-scale) or gain

(full-scale) errors.

V

V

V

V

N

OUT

REFL

REFH

REFL

=

+ (

)•

–

4096

LAYOUT

A precision analog component requires careful layout, ad-

equate bypassing, and clean, well-regulated power supplies.

As the DAC7616 offers single-supply operation, it will

often be used in close proximity with digital logic,

microcontrollers, microprocessors, and digital signal pro-

cessors. The more digital logic present in the design and the

higher the switching speed, the more difficult it will be to

keep digital noise from appearing at the converter output.

Because the DAC7616 has a single ground pin, all return

currents, including digital and analog return currents, must

flow through the GND pin. Ideally, GND should be con-

nected directly to an analog ground plane. This plane should

be separate from the ground connection for the digital

components until they were connected at the power entry

point of the system (see Figure 3).

The power applied to VDD should be well regulated and low

noise. Switching power supplies and DC/DC converters will

often have high-frequency glitches or spikes riding on the

output voltage. In addition, digital components can create

similar high-frequency spikes as their internal logic switches

states. This noise can easily couple into the DAC output

voltage through various paths between the power connec-

tions and analog output.

As with the GND connection, VDD should be connected to

a +3V power supply plane or trace that is separate from the

connection for digital logic until they are connected at the

power entry point. In addition, the 1

µF to 10µF and 0.1µF

capacitors shown in Figure 4 are strongly recommended. In

some situations, additional bypassing may be required, such

as a 100

µF electrolytic capacitor or even a “Pi” filter made

up of inductors and capacitors—all designed to essentially

lowpass filter the +3V supply, removing the high frequency

noise (see Figure 3).