50% VDD

50% VDD

CLK

Yn

tPLH

tPHL

VDD

0 V

VOL

VOH

50% VDD

50% VDD

VDD

0 V

VOL

VOH

VOL

VOH

CLK

Any Y

Any Y

tsk(o)

tsk(o)

1.7 V or 2 V

0.4 V

0.4 V

tPLH

tPHL

50% VDD

50% VDD

VDD

0 V

VOH

VOL

tr

tf

CLK

Yn

500

CL = 25 pF on Yn

From Output

Under Test

CDCVF2310

SCAS666D – JUNE 2001 – REVISED OCTOBER 2015

www.ti.com

7 Parameter Measurement Information

A.

CL includes probe and jig capacitance.

B.

All input pulses are supplied by generators having the following characteristics: PRR

≤ 200 MHz, ZO = 50 Ω,

tr < 1.2 ns, tf < 1.2 ns.

Figure 2. Test Load Circuit

Figure 3. Voltage Waveforms Propagation Delay Times

Figure 4. Output Skew

NOTE: tsk(p) = | tPLH – tPHL |

Figure 5. Pulse Skew

8

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