CD74HC4017-Q1

HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER

WITH 10 DECODED OUTPUTS

SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Qualified for Automotive Applications

D Fully Static Operation

D Buffered Inputs

D Common Reset

D Positive Edge Clocking

D Typical f

MAX = 60 MHz at VCC = 5 V,

CL = 15 pF, TA = 25°C

D Fanout (Over Temperature Range)

− Standard Outputs ... 10 LSTTL Loads

− Bus Driver Outputs ... 15 LSTTL Loads

D Balanced Propagation Delay and Transition

Times

D Significant Power Reduction Compared to

LSTTL Logic ICs

D V

CC Voltage = 2 V to 6 V

D High Noise Immunity N

IL or NIH = 30% of

VCC, VCC = 5 V

description/ordering information

The CD74HC4017 is a high-speed silicon-gate

CMOS 5-stage Johnson counter with ten decoded

outputs. Each of the decoded outputs normally is low

and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry

(TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the

clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset

(MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.

ORDERING INFORMATION{

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

40

°Cto125°C

SOIC − M

Tape and reel

CD74HC4017QM96Q1

HC4017Q

−40

°C to 125°C

TSSOP − PW

Tape and reel

CD74HC4017QPWRQ1

HC4017Q

† For the most current package and ordering information, see the Package Option Addendum at the

end of this document, or see the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

FUNCTION TABLE

INPUTS

OUTPUT STATE†

CP

CE

MR

OUTPUT STATE†

L

X

L

No change

X

H

L

No change

X

X

H

0 = H, 1−9 = L

↑

L

L

Increments counter

↓

X

L

No change

X

↑

L

No change

H

↓

L

Increments counter

NOTE: H = high voltage level, L = low voltage level,

X = don’t care,

↑ = transition from low to high

level,

↓ = transition from high to low level

† If n < 5, TC = H, otherwise TC = L

Copyright

 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

M OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

5

1

0

2

6

7

3

GND

VCC

MR

CP

CE

TC

9

4

8