CD74HC4017EP

HIGHSPEED CMOS LOGIC DECADE COUNTER/DIVIDER

WITH 10 DECODED OUTPUTS

SCLS550 − DECEMBER 2003

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of

−40

°C to 125°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree†

D Fully Static Operation

D Buffered Inputs

D Common Reset

D Positive Edge Clocking

D Typical fmax = 60 MHz at VCC = 5 V,

CL = 15 pF, TA = 25°C

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D Fanout (Over Temperature Range)

− Standard Outputs ... 10 LSTTL Loads

− Bus Driver Outputs ... 15 LSTTL Loads

D Balanced Propagation Delay and Transition

Times

D Significant Power Reduction Compared to

LSTTL Logic ICs

D VCC Voltage = 2 V to 6 V

D High Noise Immunity NIL or NIH = 30% of

VCC, VCC = 5 V

description/ordering information

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each

of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of

the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and

can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting

when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded

outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 125°C

SOIC − M

Tape and reel

CD74HC4017QM96EP

HC4017E

−40

°C to 125°C

TSSOP − PW

Tape and reel

CD74HC4017QPWREP

HC4017E

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

M OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

5

1

0

2

6

7

3

GND

VCC

MR

CP

CE

TC

9

4

8