bq2016

GAS GAUGE IC FOR

HIGH DISCHARGE RATES

SLUS475A– JANUARY 2001 – REVISED NOVEMBER 2002

18

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

To calibrate the VFC, 0x68 must be written to this location. During VFC offset calibration, the bq2016 deselects

the SR1 and SR2 inputs and disables the LEDs. When the bq2016 successfully completes VFC calibration, it

sets the OCE bit in FLAGS1. The command 0x60 terminates a VFC calibration. The bq2016 automatically

performs VFC calibration after trickle detection and initial power-up, and when NAC = LMD.

PFC (0x0f) – Programmed Full Count

The PFC register stores the battery design capacity as defined by the VPFC input.

VSB (0x10 and 0x11) – Battery Voltage

VSBH (0x11) and VSBL (0x10) form the 16-bit register that contains the voltage present at the SB input pin in

mV.

VSR (0x12 and 0x13) – Current Scale

VSRH (0x13) and VSBL (0x12) form the 16-bit register that contains the voltage present across the SR inputs

pin in mV.

TEMPV (0x14 and 0x15) – Thermistor Voltage

TEMPVH (0x15) and TEMPVL (0x14) form the 16-bit register that contains the voltage present at the TS inputs

pin in mV.

DCR (0x18) – Discharge Count Register

DCR stores the cumulative discharge count from the time VDQ is set on a charge. The data is represented in

the same units as PFC. The number of counts equals DRC

× 256.

FLAGS3 (0x4c) – Third Status Flags

The FLAGS3 register provides bq2016 status information. The 8-bit register includes the following status bits:

7

6

5

4

3

2

1

0

RSVD

RSVD

RSVD

RSVD

VQ

CR1

CR0

RSVD

CR1–CR0

The CR1–CR0 bits represent the present charge rate of the battery according to the following code:

CHARGE RATE INDICATION

CHARGE RATE (R)

CR1

CR0

R

≤ C / 8

0

0

C / 5

≥ R > C / 8

0

1

R

> C / 5

1

1

VQ

The bq2016 sets the VQ bit when it detects a valid charge condition. A valid charge is two NAC increments.

Bit = Condition

0

= No valid charge condition

1 =

Valid charge condition present