Avance Logic Inc.
ALS300
27
Pay special attention to data bus and address bus inside ALS300 because this may be the very heavy
power consumption source.
Use internal block chip select signal to be the block power control signal as much as possible.
The pull up resistors on any power up configuration pin must be disconnected from VCC after reset.
H/W power-down pin is disabled.
S/w power down mode is the same as h/w power down mode except RST and I/O access to power down
register are still enable.
The I/O access of the following register does not need power management control and must have
real time response.
POWER DOWN REGISTER
FIFO Control Attention:
Whenever new continuous DMA command for 8/16 bit wave playback is received, SB16 ESP should
always flush primary PCM FIFO.
ALS300 should has a primary FIFO r/w counter reset indicator, ISA reset or ESP RESET should reset
this indicator. When current DMA operation is 8 bit stereo or 16 bit mono, if DMA transfer times is not
even, this indicator should indicate bit 0 of FIFO r/w counter must be reset by ESP when new DMA
command is received. When current DMA operation is 16 bit stereo, if DMA transfer times is not
multiple times of 4, this indicator should indicate that bit 0 and bit 1 of FIFO r/w counter must be reset
by ESP when new DMA command is received.
Any time when new DMA command is received, this indicator must be reset after primary FIFO r/w
counter control.
MIDIOUT FIFO Size : 16 bytes
MIDIIN FIFO Size : 8 bytes
MIDIOUT RAM Size : 128 bytes
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