AMC80AIPWR datasheet(19/31 Pages) TI2

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AMC80

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SBOS559B – MAY 2011 – REVISED OCTOBER 2015

7.5.8 Input Mode Register

Table 12. Input Mode Register (Address = 09h, Default = 00h)

BIT

NAME

TYPE

DESCRIPTION

When set to '1', CH0 and CH1 operate as a differential input.

Diff01

R/W

When set to '0', CH0 and CH1 operate as 2 single-ended inputs.

When bit 0 = '1', CH0 and CH1 differential inputs are setup in normal polarity mode when

Pol01

R/W

this bit is set to '1', and in reverse polarity mode when this bit is set to '0'.

When bit 0 is set to “0”, this bit is ignored.

When set to '1', CH2 and CH3 operate as a differential input.

Diff23

R/W

When set to '0', CH2 and CH3 operate as 2 single-ended inputs.

When bit 0 = '1', CH2 and CH3 differential inputs are setup in normal polarity mode when

Pol23

R/W

this bit is set to '1', and in reverse polarity mode when this bit is set to '0'.

When bit 0 is set to “0”, this bit is ignored.

When set to '1', CH4 and CH5 operate as a differential input.

Diff45

R/W

When set to '0', CH4 and CH5 operate as 2 single-ended inputs.

When bit 0 = '1', CH4 and CH5 differential inputs are setup in normal polarity mode when

Pol45

R/W

this bit is set to '1', and in reverse polarity mode when this bit is set to '0'.

When bit 0 is set to “0”, this bit is ignored.

Reserved

R/W

'0' must be written to this bit.

Reserved

R/W

'0' must be written to this bit.

7.5.9 ADC Control Register

Table 13. ADC Control Register (Address = 0Ah, Default = 02h)

BIT

NAME

TYPE

DESCRIPTION

DR2

R/W

The 10-bit ADC conversion rate for the analog inputs is set as follows:

000 = 0.512 kHz

DR1

R/W

001 = 1 kHz

010 = 1.98 kHz

011 = 3.6 kHz

100 = 6.3 kHz

DR0

R/W

101 = 9.8 kHz

110 = 13.15 kHz

111 = 13.15 kHz

PGA2

R/W

The full-scale analog input range is set as follows:

000 = 2.56 V

PGA1

R/W

001 = VDD

010 = 4.096 V or VDD (whichever is less)

011 = 2.048 V

100 = 1.024 V

PGA0

R/W

101 = 0.512 V

110 = 0.256 V

111 = 0.256 V

Reserved

R/W

'0' must be written to this bit.

Reserved

R/W

'0' must be written to this bit.

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