ADF4378 datasheet(11/84 Pages) AD

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Data Sheet

ADF4378

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. A | 11 of 84

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin Number

Mnemonic

Description

1, 2, 4, 10, 12,

14, 16, 18, 19,

21, 23, 25, 26,

41, 48

GND

Negative Power Supply (Ground). These pins must be connected directly to the ground pad.

V3_NDIV

3.15 V to 3.45 V Positive Power Supply Pin for the PLL Feedback Divider Circuitry. Short this pin to the other pins in 3.3 V Power Supply

Group 1.

V3_VCO

3.15 V to 3.45 V Positive Power Supply Pin for the 3.3 V Portion of the VCO Circuitry. Short this pin to the other pins in 3.3 V Power

Supply Group 2.

DCLBIAS

Do not connect to this pin.

VTUNE

VCO Tuning Input. This frequency control pin is normally connected to the external loop filter.

V5_CAL

4.75 V to 5.25 V Positive Power Supply Pin for VCO Calibration Circuitry. This pin can be shorted to the V5_VCO supply plane.

V5_VCO

4.75 V to 5.25 V Positive Power Supply Pin for the 5 V Portion of the VCO Circuitry.

V3_CLKDIV

3.15 V to 3.45 V Positive Power Supply Pin for the Output Divider Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.

V3_SROUT

3.15 V to 3.45 V Positive Power Supply Pin for the SYSREF Buffer Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group

15, 17

SR_OUTN,

SR_OUTP

SYSREF Output Signal. The reclocked SYSRREF input is presented differentially on these pins. The outputs have 50 Ω (typical) output

resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the

outputs. Typically, these outputs have a 1.2 V common mode and are designed to interface with an LVDS input. However, there are

termination schemes that allow for other common levels.

20, 22

CLKN, CLKP

Clock Output Signal. The VCO output divider is buffered and presented differentially on these pins. The outputs have 50 Ω (typical) output

resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the

outputs. The output amplitude is programmable through the serial port.

V3_CLK

3.15 V to 3.45 V Positive Power Supply Pin for the Clock 1 Buffer Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.

LKDET

PLL Lock Detect. This output presents the lock status of the PLL. The PLL is locked when the LKDET pin is a logic high.

ENSR

Enable SYSREF Output Buffer. 1.8 V and 3.3 V compatible CMOS input. When ENSR = high, the SR_OUTP and SR_OUTN output buffer

is active. When ENSR = low, SR_OUTP and SR_OUTN output buffer is powered down.

ENCLK

Enable Clock 1 Output Buffer. 1.8 V and 3.3 V compatible CMOS input. When ENCLK = high, the CLKP and CLKN output buffer is active.

When ENCLK = low, the CLKP and CLKN output buffer is powered down.

V3_LS

3.15 V to 3.45 V Positive Power Supply Pin for the Internal Level Shift Circuitry. Short this pin to the other pins in 3.3 V Power Supply

Group 1.

Chip Enable. 3.3 V CMOS input. Does not support 1.8 V CMOS levels. This CMOS input enables the device when driven high. A logic low

disables the device, putting the device in a full power-down state, which causes the registers to reset. Conversely, the PD_ALL bit powers

down the device, but does not reset the registers.

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