ADE9112 datasheet(15/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. A | 15 of 55

Table 11. ADE9103 Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

VLDOOUT

1.8 V Output of Digital LDO Regulator. Decouple the VLDOOUT pin with a 4.7 µF capacitor in parallel with a ceramic 100 nF

capacitor to DGND, Pin 25. Do not connect the external load circuitry to the VLDOOUT pin.

XTALOUT

Crystal Output. A crystal must be chosen based on the transconductance (gm) in Table 2. The crystal is connected across

the XTALIN and XTALOUT pins to provide a clock source for the ADE9103. The XTALOUT pin must float when unused.

XTALIN

Main Clock Input. An external clock can be provided at this logic input. The CLKOUT signal of another appropriately

configured ADE9103/ADE9112/ADE9113 (see the Synchronizing Multiple ADE9103/ADE9112/ADE9113 Devices section for

details) can be provided at the XTALIN pin. Alternatively, a crystal can be connected across XTALIN and XTALOUT to

provide a clock source for the ADE9103. See the Crystal Oscillator/External Clock section for more details.

RESET

Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for a minimum of 1.5 μs.

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